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throttle cont rol h-bridge 33931 ordering information device (add r2 suffix for tape and reel) temperature range (t a ) package MC33931VW -40 to 125c 44 hsop mc33931ek 32 soicw-ep vw suffix (pb-free) 98arh98330a 44-pin hsop with protruding heat sink ek suffix (pb-free) 98arl10543d 32-pin soicw-ep document number: mc33931 rev. 4.0, 10/2012 freescale semiconductor technical data ? freescale semiconductor, inc. , 2008-2012. all rights reserved. 5.0 a throttle control h-bridge the 33931 is a monolithic h-bridge power ic in a robust thermally enhanced package. it is designed primarily for automotive electronic throttle control, but is applicable to any low voltage dc servo motor control application within the current and voltage limits stated in this specification. the 33931 h-bridge is able to control inductive loads with currents up to 5.0 a peak. rms current capability is subject to the degree of heatsinking provided to the devic e package. internal peak-current limiting (regulation) is activated at load currents above 6.5 a 1.5 a. outp ut loads can be pulse-width mo dulated (pwm-ed) at frequencies up to 11 khz. a load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller?s a/d input. a status flag output reports under-voltage, over-current, and over-temperature fault conditions. two independent inputs provide polarity control of two half-bridge totem-p ole outputs. the disable inputs are provided to force the h- bridge outputs to tri-state (high-impedance off-state). features ? 5.0 to 28 v continuous operation (trans i ent operation from 5.0 to 40 v) ?235 m maximum r ds(on) @ t j =150 c (each h-bridge mosfet) ?3.0 v and 5.0 v ttl / cmos logic compatible inputs ? over-current limiting (regulation) via internal constant-off-time pwm ? output short-circuit protection (short to vpwr or gnd) ? temperature-dependant current-limit th reshold reduction ? all inputs have an internal source/sink to define the default (flo ating input) states ? sleep mode with current draw < 50 a sf fb in1 in2 d1 en/d2 vpwr ccp out1 out2 pgnd agnd mcu 33931 v pwr v dd motor figure 1. mc33931 simpli fied application diagram
analog integrated circuit device data 2 freescale semiconductor 33931 internal block diagram internal block diagram vdd logic supply charge pump gate drive and protection logic current mirror and constant off-time pwm current regulator vcp ccp out1 out2 pgnd to gates hs1 ls1 hs2 ls2 vpwr vsense ilim pwm hs1 hs2 ls1 ls2 ls2 in1 in2 en/d2 d1 sf fb agnd pgnd figure 2. 33931 simplifi ed internal block diagram
analog integrated circuit device data freescale semiconductor 3 33931 pin connections pin connections tab tab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 d1 fb en/d2 vpwr vpwr vpwr out1 out1 pgnd pgnd sf in1 in2 ccp vpwr vpwr out2 out2 out2 pgnd pgnd 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c agnd 44 hsop transparent top view 32 soicw-ep transparent top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 d1 fb en/d2 vpwr vpwr vpwr out1 out1 out1 pgnd pgnd n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c sf in1 in2 ccp vpwr out2 out2 pgnd pgnd 32 31 30 29 28 27 26 25 24 23 n/c n/c agnd figure 3. 33931 pin connections table 1. 33931 pi n definitions a functional description of each pin can be found in the functional description section beginning on page 11 . pin hsop (vw) pin soicw-ep (ek ) pin name pin function formal name definition 1 2 d1 logic input disable input 1 (ac tive high) when d1 is logic high, both out1 and out2 are tri-stated. schmitt trigger input with ~80 a source so default condition = disabled. 2 3 fb analog output feedback the load current feedback output provides ground referenced 0.24 % of the high side output current. (tie to gnd through a resistor if not used.) 3 5 en/ d2 logic input enable input when en/ d2 is logic high the h-bridge is operational. when en/ d2 is logic low, the h-bridge outputs are tri-stated and placed in sleep mode. (logic input with ~ 80 a sink so de fault condition = sleep mode.) 4-6, 40, 39 7, 8, 25, 26 v pwr power input positive power supply these pins must be connected t ogeth er physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the pcb. 7-9 10, 11 out1 power output h-bridge output 1 source of hs1 and drain of ls1. 10, 11, 34, 35 15-18 pgnd power ground power ground high-current power ground pins must be connected together physically as close as p ossible and directly soldered down to a wide, thick, low resistance ground plane on the pcb. 36-38 22, 23 out2 power output h-bridge output 2 source of hs2 and drain of ls2.
analog integrated circuit device data 4 freescale semiconductor 33931 pin connections 41 28 ccp analog output charge pump capacitor external reservoir capacitor c onnection for the internal charge pump; connected to vpwr. allowable values are 30 nf to 100 nf. note: this capacitor is required for the proper performance of the device. 42 29 in2 logic input input 2 logic input control of out2;e.g., when in2 is logic high, out2 is set to vpwr, and when in2 is logic low, out2 is set to pgnd. (schmitt trigger input with ~ 80 p a source so default condition = out2 high.) 43 31 in1 logic input input 1 logic input control of out1; e.g., when in1 is logic high, out1 is set to vpwr, and when in1 is logic low, out1 is set to pgnd. (schmitt trigger input with ~ 80 p a source so default condition = out1 high.) 44 32 sf logic output - open drain status flag (active low) open drain active low status flag output (requires an external pull-up resistor to v dd . maximum permissible load current < 0.5 ma. maximum v sf low < 0.4 v @ 0.3 ma. maximum permissible pull-up voltage < 7.0 v.) tab 1 agnd analog ground analog signal ground the low-current analog signal ground must be connected to pgnd via low-impedance path (<10 m : , 0 hz to 20 khz). 12-33 4, 6, 9, 12-14, 19-21, 24, 27, 30 n/c none no connect pin is not used ep ep thermal pad exposed pad exposed tab is also the main heatsinking path for the device and must be connected to gnd. table 1. 33931 pin definitions (continued) a functional description of each pin can be found in the functional description section beginning on page 11 . pin hsop (vw) pin soicw-ep (ek) pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33931 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to grou nd, unless otherwise noted. exceeding these ratings may cause a malfunction or permanent damage to the device. thes e parameters are not production tested. ratings symbol value unit electrical ratings power supply voltage normal operation (steady-state) transient over-voltage (1) pwr(ss) pwr(t) - 0.3 to 28 - 0.3 to 40 v logic input voltage (2) v in - 0.3 to 7.0 v sf output (3) v sf - 0.3 to 7.0 v continuous output current (4) i out(cont) 5.0 a esd voltage (5) human body model machine model charge device model corner pins all other pins v esd1 v esd2 2000 200 750 500 v thermal ratings storage temperature t stg - 65 to 150 c operating temperature (6) ambient junction t a t j - 40 to 125 - 40 to 150 c peak package reflow temperature during reflow (7) , (8) t pprt note 8 c approximate junction-to-case thermal resistance (9) r jc < 1.0 c/w notes 1. device will survive repetitive transient over-v o ltage conditions for durations not to exceed 500 ms @ duty cycle not to exceed 10%. external protection is required to prevent device damage in case of a reverse battery condition. 2. exceeding the maximum input voltage on in1, in2, en/ d2 or d1 may cause a malfunction or permanent damage to the device. 3. exceeding the pull-up resistor voltage on the open drain sf pin may cause permanent damage to the device. 4. continuous output current capability is dependent on sufficient package heatsin king to keep junction temperature 150 c. 5. esd testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ), mach ine model (c zap = 200 pf, r zap = 0 ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 6. the limiting factor is junction temperatur e , taking into account the power dissipation, thermal resistance, and heat sinking provided. brief non-repetitive excursions of junction temperature above 150 c can be tolerated, provided the duration does not exceed 30 seconds maximum. (non-repetitive events are defined as not occurring more than once in 24 hours.) 7. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 8. freescale?s package reflow capability m eets p b-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by par t number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. ( i.e. mc33xxxd enter 33xxx), and review parametrics. 9. exposed heatsink pad plus the power and ground pins comp rise the main heat conduc tion paths. the actual r jb (junction-to-pc board) values will vary depending on solder thickness and composition and copper trace thickness and area. maximum current at maximum die temperature represents ~16 w of conduction loss heating in the diagonal p air of output mosfets. therefore, the r ja must be < 5.0 c /w for maximum current at 70 c amb ient. module thermal design must be planned accordingly. v v
analog integrated circuit device data 6 freescale semiconductor 33931 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 5.0 v d v pwr d 28 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power inputs (vpwr) operating voltage range (10) steady-state transient (t < 500 ms) (11) v pwr(ss) v pwr(t) 5.0 ? ? ? 28 40 v sleep state supply current (12) en/ d2 = logic [0], in1, in2, d1 = logic [1], and i out = 0a i pwr(sleep) ? ? 50 p a standby supply current (part enabled) i out = 0 a, v en = 5.0 v i pwr(standby) ? ? 20 ma under-voltage lockout thresholds v pwr(falling) v pwr(rising) hysteresis v uvlo(active) v uvlo(inactive) v uvlo(hys) 4.15 ? 150 ? ? 200 ? 5.0 350 v v mv charge pump charge pump voltage (cp capacitor = 33 nf), no pwm v pwr = 5.0 v v pwr = 28 v v cp - v pwr 3.5 ? ? ? ? 12 v charge pump voltage (cp capacitor = 33 nf), pwm = 11 khz, v pwr = 5.0 v v pwr = 28 v v cp - v pwr 3.5 ? ? ? ? 12 v control inputs operating input voltage (in1, in2, d1, en/ d2 ) v i ? ? 5.5 v input voltage (in1, in2, d1, en/ d2 ) logic threshold high logic threshold low hysteresis v ih v il v hys 2.0 ? 250 ? ? 400 ? 1.0 ? v v mv logic input currents, vpwr = 5.0 v input en/ d2 (internal pull-downs), v ih = 5.0 v inputs in1, in2, d1 (internal pull-ups), vil = 0 v i in 20 -200 80 -80 200 -20 p a notes 10. device specifications are char acterized over the range of 8.0 v d v pwr d 28 v. continuous operation above 28 v may degrade device reliability. device is operational down to 5.0 v, but below 8.0 v the output resistance may increase by 50 percent. 11. device will survive the tr ansient over-voltage indicated for a maximum duration of 500 ms. transient not to be repeated more than once every 10 seconds. 12. i pwr(sleep) is with sleep mode activated and en/ d2 , = logic [0], and in1, in2, d1 = logi c [1] or with these inputs left floating.
analog integrated circuit device data freescale semiconductor 7 33931 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics power outputs out1, out2 output-on resistance (14) , i load = 3.0 a v pwr = 8.0 v, t j = 25 q c v pwr = 8.0 v, t j = 150 q c v pwr = 5.0 v, t j = 150 q c r ds(on) ? ? ? 120 ? ? ? 235 325 m : output current regulation threshold t j < t fb t j t t fb (foldback region - see figure 9 and figure 11 ) (13) i lim 5.2 ? 6.5 4.2 8.0 ? a high side short circuit detection threshold (short circuit to ground) (13) i sch 11 13 16 a low side short circuit detection threshold (short circuit to v pwr ) (13) i scl 9.0 11 14 a output leakage current (15) , outputs off, v pwr = 28 v v out = v pwr v out = ground i outleak ? -60 ? ? 100 ? p a output mosfet body diode forward voltage drop, i out = 3.0 a v f ? ? 2.0 v over-temperature shutdown (13) thermal limit @ t j hysteresis @ t j t lim t hys 175 ? ? 12 200 ? q c current foldback at t j (13) t fb 165 ? 185 q c current foldback to thermal shutdown separation (13) t sep 10 ? 15 q c high side current sense feedback feedback current (pin fb sourcing current) (16) i out = 0 ma i out = 300 ma i out = 500 ma i out = 1.5 a i out = 3.0 a i out = 6.0 a i fb 0.0 0.0 0.35 2.86 5.71 11.43 ? 270 0.775 3.57 7.14 14.29 50 750 1.56 4.28 8.57 17.15 p a p a ma ma ma ma status flag (17) status flag leakage current (18) v sf = 5.0 v i sf leak ? ? 5.0 p a status flag set voltage (19) i sf = 300 a v sf low ? ? 0.4 v notes 13. this parameter is guaranteed by design. 14. output-on resistance as measured from output to v pwr and from output to gnd. 15. outputs switched off via d1 or en/ d2 . 16. accuracy is better than 20% from 0.5 a to 6.0 a. recommended terminating resistor value: r fb = 270 : 17. status flag output is an open drain output requiring a pull-up resistor to logic v dd . 18. status flag leakage current is measured with status flag high and not set. 19. status flag set voltage measured with status flag low and set with i sf = 300 p a. maximum allowable sink current from this pin is < 500 p a . maximum allowable pull-up voltage < 7.0 v. table 3. static electrical characteristics (continued) characteristics noted under conditions 5.0 v d v pwr d 28 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
table 4. dynamic electri cal cha racteristics characteristics noted under conditions 5.0 v v pwr 28 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical valu es noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (20) f pwm ? ? 11 khz maximum switching frequency during current limit regulation (21) f max ? ? 20 khz output on delay (22) pwr v t don ? ? 18 s output off delay (22) pwr v t doff ? ? 12 s i lim output constant-off time (23) (25) t a 15 20.5 32 s i lim blanking time (24) (25) t b 12 16.5 27 s disable delay time (26) t ddisable ? ? 8.0 s output rise and fall time (27) t f , t r 1.5 3.0 8.0 s short-circuit / over-temperature turn-off (latch-off) time (28) , (29) t fault ? ? 8.0 s power-on delay time (29) t pod ? 1.0 5.0 ms output mosfet b ody diode reverse recovery time (29) t r r 75 100 150 ns charge pump operating frequency (29) f cp ? 7.0 ? mhz notes 20. the maximum pwm frequency should be limited to frequencies < 11 khz in order to allow the internal high side dr iver circuitry time to fully enhance the high side mosfets. 21. the internal current limit circuitry produces a constant-off - time pulse width modulation of the output current. the output l oad?s inductance, capacitance, and resistance char acteristics affect the total switching period (off-time + on-time), and thus the pw m frequency during current limit. 22. * ou tput delay is the time duration from 1.5 v on the in1 or in2 input signal to the 20% or 80% point (dependent on the transition direction) of the out1 or out2 signal. if the output is tr ansitioning high-to-low, the delay is from 1.5 v on the input signal to the 80% point of the output response signal. if the output is trans itioning low-to-high, the delay is from 1.5 v on the input signal to the 20% point of the output r esponse signal. see figure 4 , page 9 . 23. the time during which the internal constant-off t ime pwm current regulation circuit has tri-stated the output bridge. 24. the time during which the current regulation threshold is i gnored so that the short-circuit detection threshold comparators may have time to act. 25. parameter is guaranteed by characterization. 26. * disable delay time measureme nt is defined in figure 5 , page 9 . 27. rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal with v pwr r load = 3.0 ohm. see figure 6 , page 9 . 28. load currents ramping up to the current r egulation threshold become limited at th e i lim value (see figure 7 ). the short-circuit currents possess a di/dt that ramps up to the i sch or i scl threshold during the i lim blanking time, registering as a short-circuit event detection and causing the shutdown circuitry to force the out put into an immediate tri-state latch-off (see figure 8 ). operation in current limit mode may cause junction temperatures to ri se . junction temperatures above ~160 c will cause the output current limit threshold to ?fold back?, or decrease, until ~175 c is reached, after which the t lim thermal latch-off will occur. permissibl e operation within this fold back region is limited to non-repetitive transient event s of duration not to exceed 30 seconds (see figure 9 ). 29. parameter is guaranteed by design. analog integrated circuit device data 8 freescale semiconductor 33931 electrical characteristics dynamic electrical characteristics v = 14 v = 14 = 14 v,
analog integrated circuit device data freescale semiconductor 9 33931 electrical characteristics timing diagrams timing diagrams 5.0 v pwr 0 0 time 1.5 v 1.5 v 20% 80% t don v out1, 2 (v) v in1, in2 (v) t doff figure 4. output delay time 0v 5.0 v 0? v out1, 2 v d1, en/d2 (v) time 1.5 v t ddisable 90% i o = 100 ma figure 5. disable delay time . 90% 90% 10% 10% v out1, 2 (v) t f t r v pwr 0 time figure 6. output switching time i sc short-circuit detection threshold i out , current (a) t b 5.0 t a 9.0 0.0 i lim 6.5 t b = i lim blanking time t a = constant-off time (out1 and out2 tri-stated) overload condition t on time figure 7. current limit blanking time and constant-off time
i sc short-circuit detection threshold i out , current (a) 5.0 9.0 0.0 i lim 6.5 hard short occurs t fault short-circuit condition t b (~16 s) t b time sf set low out1, out2 tri-stated, analog integrated circuit device data 10 freescale semiconductor 33931 electrical characteristics timing diagrams figure 8. short-circuit detection turn-off time t fault . current limit threshold foldback. i lim , current (a) 6.5 4.2 t lim t fb t hys t sep t lim thermal shutdown operation within this region must be limited to non-repetitive events not to exceed 30 s per 24 hr. figure 9. output current limiting foldback region
analog integrated circuit device data freescale semiconductor 11 33931 functional description introduction functional description introduction numerous protection and operational features (speed, torque, direction, dynamic breaking, pwm control, and closed-loop control) make the 33931 a very attractive, cost- effective solution for controlling a broad range of small dc motors. the 33931 outputs are capable of supporting peak dc load currents of up to 5.0 a from a 28 v v pwr source. an internal charge pump and gate drive circuitry are provided that can support external pwm frequencies up to 11 khz. the 33931 has an analog feedback (current mirror) output pin (the fb pin) that provides a constant-current source ratioed to the active high side mosfet s ? current. this can be used to provide ?real time? mo nitoring of output current to facilitate closed-loop operat ion for motor speed/torque control, or for the detection of open load conditions. two independent inputs, in1 and in2, provide control of the two totem-pole half-bridge outputs. two independent disable inputs, d1 and en/ d2 , provide the means to force the h-bridge outputs to a high-im pedance state (all h-bridge switches off). the en/ d2 pin also controls an enable function that allows the ic to be placed in a power-conserving sleep mode. the 33931 has output current lim iting (via constant off- time pwm current regu lation), output short-circuit detection with latch-off, and over-tem perature detection with latch- off. once the device is latched-off due to a fault condition, either of the disable inputs (d1 or en/ d2 ), or v pwr must be ?toggled? to clear the status flag. current limiting (load current regulation) is accomplished by a constant-off time pwm method using current limit threshold triggerin g. the current limiting scheme is unique in that it incorpor ates a junction temperature- dependent current limit threshold. this means that the current limit threshold is ?reduced to around 4.2 a? as the junction temperature increases above 160 c. when the temperature is above 175 c, over-temperature shutdown (latch-off) will occur. this co mbination of features allows the device to continue operating for short periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. functional pin description power ground and analog ground (pgnd and agnd) the power and analog ground pins should be connected together with a very low-impedance connection. positive power supply (vpwr) vpwr pins are the power supply inputs to the device. all vpwr pins must be connected together on the printed circuit board with as short as possible traces, offering as low an impedance as possible between pins. status flag ( sf ) this pin is the device fault st atus output. this output is an active low open drain structure requiring a pull-up resistor to v dd . the maximum v dd is < 7.0 v. refer to table 5 , for the sf output status definition. input 1,2 and disable input 1 (in1, in2, and d1 ) these pins are input control pins used to control the outputs. these pins are 3.0 v/ 5.0 v cmos-compatible inputs with hysteresis. in1 and in2 independently control out1 and out2, respectively. d1 input is used to tri-state disable the h-bridge outputs. when d1 is set (d1 = logic high) in the disable state, outputs out1 and out2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply i pwr(standby) current is reduced to a few ma. refer to table 3, static electrical characteristics , page 6 . h-bridge output (out1, out2) these pins are the outputs of th e h-bridge with integrated free-wheeling diodes. the bridge output is controlled using the in1, in2, d1, and en/ d2 inputs. the outputs have pwm current limiting above the i lim threshold. the outputs also have thermal shutdown (tri-state latch-off) with hysteresis as well as short-circuit latch-off protection. a disable timer (time t b ) is incorporated to distinguish between load currents that are higher than the i lim threshold and short-circuit currents. this timer is activated at each output transition. charge pump capacitor (ccp) this pin is the charge pump ou tput pin and connection for the external charge pump reservoir capacitor. the allowable value is from 30 nf to 100 nf. this capacitor must be connected from the ccp pin to the vpwr pin. the device cannot operate properly wit hout the external reservoir capacitor. enable input/disable input 2 (en/ d2 ) the en/ d2 pin performs the same function as d1 pin, when it goes to a logic low the outputs are immediately tri- stated. it is also used to place the device in a sleep mode so as to consume very low currents. when the en/ d2 pin voltage is a logic low state, the device is in the sleep mode.
analog integrated circuit device data 12 freescale semiconductor 33931 functional description functional internal block description the device is enabled and fully operational when the en pin voltage is logic high. an internal pull-down resistor maintains the device in sleep mode in the event en is driven through a high-impedance i/o or an unpowered microcontroller, or the en/ d2 input becomes disconnected. feedback (fb) the 33931 has a feedback output (fb) for ?real time? monitoring of h-bridge high side output currents to facilitate closed-loop operation for motor speed and torque control. the fb pin provides current sensing feedback of the h-bridge high side drivers. when running in the forward or reverse direction, a ground-ref erenced 0.24% of load current is output to this pin. through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can ?read? the current proportional voltage with its analog-to-digital converter (adc). this is intended to provide the user with only first-order motor current feedback for motor torque control. the resistance range for the linear operation of the fb pin is 100 < r fb < 300 . if pwm-ing is implemented using the disable pin input (only d1), a small filter capacitor (~1.0 f) may be required in parallel with the r fb resistor to ground for spike suppression. functional internal block description mcu interface 33931 protection logic control fault logic gate control logic current sense voltage regulation temperature sense charge pump h-bridge output drivers out1 - out2 analog control and protection input logic control figure 10. functional internal block diagram analog control and protection circuitry: an on-chip voltage regulator supplies the internal logic. the charge pump provides gate drive for the h-bridge mosfets. the current and temperature sense circuitry provides detection and protecti on for the output drivers. output under-voltage protection shuts down the mosfets. gate control logic: the 33931 is a monolithic h-bridge power ic designed primarily for any low-voltage dc servo motor control application within the current and voltage limits stated for the device. two independent inputs provide polarity control of two half-bridge totem-pole outp uts. two independent disable inputs are provided to force the h-bridge outputs to tri-state (high-impedance off-state). h-bridge output drivers: out1 and out2 the h-bridge is the power output stage. the current flow from out1 to out2 is reversible and under full control of the user by way of the input contro l logic. the output stage is designed to produce full lo ad control under all system conditions. all protective and co ntrol features are integrated into the control and protection blocks. the sensors for current and temperature are integrated directly into the output mosfet for maximum accuracy and dependability.
analog integrated circuit device data freescale semiconductor 13 33931 functional device operation operational modes functional device operation operational modes pwm current limiting 9.0 6.5 typical short-circuit detection threshold typical current limit threshold hard short detect ion and latch-off 0 in1 or in2 in2 or in1 in1 or in2 in2 or in1 in1 in2 [1] [0] [1] [0] [1] [0] [1] [0] outputs tri-stated outputs tri-stated outputs operation (per input control condition) time sf logic out en/d2 logic in d1 logic in in n logic in i load output current (a) high current load being regulated via constant-off-time pwm moderate current load figure 11. operating states
analog integrated circuit device data 14 freescale semiconductor 33931 functional device operation logic commands logic commands table 5. truth table the tri-state conditions and the statu s flag are reset using d1 or en/ d2 . the truth table uses the fo llowing notations: l = low, h = high, x = high or low, and z = high-impedance . all output power transistors are switched off. device state input conditions status outputs en/ d2 d1 in1 in2 sf out1 out2 forward h l h l h h l reverse h l l h h l h freewheeling low h l l l h l l freewheeling high h l h h h h h disable 1 (d1) h h x x l z z in1 disconnected h l z x h h x in2 disconnected h l x z h x h d1 disconnected h z x x l z z under-voltage lockout (30) h x x x l z z over-temperature (31) h x x x l z z short-circuit (31) h x x x l z z sleep mode en/ d2 l x x x h z z en/ d2 disconnected z x x x h z z notes 30. in the event of an under-voltage condition, the outputs tr i-state and status fla g is set logic low. upon under-voltage recovery, status flag is reset automatically or automatically cleared and the output s are restored to their original operating condition. 31. when a short-circuit or over-temperat ure condition is d etected, the power outputs are tri-state latched-off independent of the input signals and the status flag is latc hed to logic low. to reset from this condi tion requires the toggling of either d1, en/ d2 , or v pwr . out1 out2 pgnd v pw r v pw r pgnd load load current forward off on on off out1 out2 pgnd off on on off v pwr v pw r pgnd load load current reverse out1 out2 pgnd v pwr v pwr pgnd load load current high-side recirculation (forward) on off on off out1 out2 pgnd v pwr v pwr pgnd load load current low-side recirculation (forward) on on off off figure 12. 33931 power stage operation protection and diagnostic features short-circuit protection if an output short-circuit c ondition is detected, the power outputs tri-state (latch-off) independent of the input (in1 and in2) states, and the fault status output flag ( sf ) is set to logic low. if the d1 input changes from logic high to logic low, or if the en/ d2 input changes from logic low to logic high, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic high state.
analog integrated circuit device data freescale semiconductor 15 33931 functional device operation protection and di agnostic features the output stage will always switch into the mode defined by the input pins (in1, in2, d1, and en/ d2 ), provided the device junction temperature is within the specified operating temperature range. internal pwm current limiting the maximum current flow under normal operating conditions should be less than 5.0 a. th e instantaneous load currents will be limited to i lim via the internal pwm current limiting circuitry. when the i lim threshold current value is reached, the output stages are tri-stated for a fixed time (t a ) of 20 s typical. depending on the time constant associated with th e load characteristics, the output current decreases during the tri-state duration un til the next output on cycle occurs. the pwm current limit threshol d value is dependent on the device junction temperature. when - 40 c < t j < 160 c, i lim is between the specified minimum/maximum values. when t j exceeds 160 c, the i lim threshold decreases to 4.2 a. shortly above 175 c the device over-temperature circuit will detect t lim and an over-temperature shutdown will occur. this feature implements a graceful degradation of operation before thermal shutdown occurs, thus allowing for intermittent unexpected mechanical loads on the motor?s gear-reduction train to be handled. important die temperature excursions above 150 c are permitted only for non-repetitive durations < 30 seconds. provision must be made at th e system level to prevent prolonged operation in the current-foldback region. over-temperature shutdown and hysteresis if an over-temperature conditi on occurs, the power outputs are tri-stated (latched-off) and the fault status flag ( sf ) is set to logic low. to reset from this condition, d1 must change from logic hig h to logic low, or en/ d2 must change from logic low to logic high. when reset, the output stage switches on again, provided that the junc tion temperature is now below the over-temperature threshold limit minus the hysteresis. important resetting from the fault condition will clear the fault status flag . powering down and powering up the device will also reset the 33931 from the fault condition. output avalanche protection if vpwr were to become an open circuit, the outputs would likely tri-state simultaneous ly due to the disable logic. this could result in an unclamped inductive discharge. the vpwr input to the 33931 should not exceed 40 v during this tr ansient condition, to prevent electrical overstress of the output drivers.this can be accomplished with a zener clamp or mov, and/or an appropriately valued input capacitor with sufficiently low esr (see figure 13 ). out1 out2 i/os agnd pgnd bulk low esr cap. vpwr 100nf m v pwr 9 figure 13. avalanche protection
analog integrated circuit device data 16 freescale semiconductor 33931 typical applications introduction typical applications introduction a typical application schematic is shown in figure 14 . for precision high-current applic ation s in harsh, noisy environments, the v pwr by-pass capacitor may need to be substantially larger. vdd logic supply charge pump gate drive and protection logic current mirrors and constant off-time pwm current regulator vcp ccp out1 out2 agnd to gates hs1 ls1 hs2 ls2 vpwr vsense ilim pwm hs1 hs2 ls1 ls2 ls2 in1 in2 en/d2 d1 sf fb pgnd +5.0 v r fb 270 status flag to adc 1.0 f 33nf v pwr 100 nf 100 f m pgnd figure 14. 33931 typical application schematic
analog integrated circuit device data freescale semiconductor 17 33931 packaging package dimensions packaging package dimensions for the most current pa ckage revision, visit www.freescale.com and perform a keyword sear ch using the 98axxxxxxxxx listed on the following pages. vw suffix 44-pin 98arh98330a revision b dimensions shown are provided for reference only.
vw suffix 44-pin 98arh98330a revision b analog integrated circuit device data 18 freescale semiconductor 33931 packaging package dimensions
ek suffix 32-pin 98arl10543d revision d analog integrated circuit device data freescale semiconductor 19 33931 packaging package dimensions
ek suffix 32-pin 98arl10543d revision d analog integrated circuit device data 20 freescale semiconductor 33931 packaging package dimensions
ek suffix 32-pin 98arl10543d revision d analog integrated circuit device data freescale semiconductor 21 33931 packaging package dimensions
analog integrated circuit device data 22 freescale semiconductor 33931 additional documentation package dimensions additional documentation thermal addendum introduction this thermal addendum is provided as a supplement to t he mc339 31 technical datasheet. the addendum provides thermal performance information that may be critical in the design and development of system applications. all el ectrical, application, and packaging information is provided in the datasheet. package and thermal considerations the mc33931 is offered in a 32-pin soicw-ep and a 44-pin hsop sing le die package. there is a single heat source (p), a single junction temperature (t j ), and thermal resistance (r ja ). this thermal addendum is sp ecific to the 32-pin soicw-ep package. the stated values are solely for a thermal performance comparison of one package to another in a standard ized environment. this methodology is not meant to, and will not predict the perf ormance of a package in an appl ication-specific environment. stated values were obtained by measurement and simulation according to the standards listed below. table 6. table of thermal resistance data rating value unit notes junction to ambient natural convection single layer board (1s) r ja 92 c/w (32) , (33) junction to ambient natural convection four layer board (2s2p) r ja 26.6 c/w (32) , (34) junction to board r jb 7.0 c/w (35) junction to case (bottom / flag) r jc (bottom) 0.62 c/w (38) junction to case (top) r jc (top) 23.3 c/w (36) junction to package top natural convection jt 2.7 c/w (37) notes 32. junction temperature is a function of die size, on-chip power dissipation, packa ge thermal re sistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 33. per jedec jesd51-2 with the singl e layer board (jesd51-3) horizontal. 34. per jedec jesd51-6 with the board (jesd51-7) horizontal. 35. thermal resistance between the die and the printed circuit board per jedec jesd51-8 . board temperature is measured on the to p surface of the board near the package. 36. thermal resistance between the die and the case top surface as measure d by the cold plate method (mil spec-883 method 1012.1 ). 37. thermal characterization parameter indicating the temperat ure differ ence between package top and the junction temperature pe r jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. 38. thermal resistance between the die and the case bottom / flag su r face (simulated) (flag bottom side fixed to ambient tempera ture). t j = r ja . p
0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000 10000 t h e r m a l ? r e s i s t a n c e ? [ c / w ] time ? [s] thermal resistance [c/w] analog integrated circuit device data freescale semiconductor 23 33931 thermal addendum package dimensions figure 15. transient thermal resistance r t ja mc33931ek on 2s2p test board
analog integrated circuit device data 24 freescale semiconductor 33931 reference section package dimensions reference section table 7. thermal analysis reference documents reference description an4146 thermal modeling and simulation of 12 v gen3 extreme switch devices with spice basicthermalwp basic principles of thermal a nalysis for semiconductor systems
analog integrated circuit device data freescale semiconductor 25 33931 revision history revision history revision date description 1.0 2/2008 ? initial release 2.0 12/2008 ? updated freescale for and style ? removed pc33931vw/r2 from the ordering information and added MC33931VW/r2 ? changes max r ds(on) from 225 to 235 mohm in the document ? changed peak package reflow temperature during reflow (7) , (8) ? changed approximate junction-to-case thermal resistance (9) ?in short-circuit protection , changed d2 to en/ d2 3.0 6/2012 ? added pc33931ek to the ordering information table ? added ek ordering and package information ? added thermal addendum and reference document sections ? minor corrections throughout the document. 4.0 10/2012 ? pc33931ek changed to mc33931ek and released to production ? document level changed from advance information to technical data ? changed soic to soicw-ep
document number: mc33931 rev. 4.0 10/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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